The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
In semiconductor technology, an integrated circuit pattern can be formed on a substrate using various processes including a photolithography process, ion implantation, deposition and etch. Damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a damascene process, trenches are formed in a dielectric material layer, copper or tungsten is filled in the trenches, then a chemical mechanical polishing (CMP) process is applied to remove excessive metal on the dielectric material layer and planarize the top surface. Studies and researches have been conducted to search, new conductive, dielectric materials, and new process integration schemes for a better interconnection. New interconnection materials, such as integrating copper metallurgy in place of traditional aluminum can be used to reduce the resistance component of the RC time delay. New insulating material with a lower dielectric constant (k) than the incumbent silicon dioxide can be applied to reduce the capacitance component as well as cross-talk between conductive lines to minimize time delay and power dissipation. In addition, metal capping or silicide capping can be used to overcome the reliability problem caused by the dimensions scaling down.
Although existing approaches have been generally serving their intended purposes, they have not been entirely satisfactory in all respects. Accordingly, a semiconductor structure including a cap layer and a method making the same are needed.